1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and more particularly to a manufacturing method of a semiconductor device, for limiting: the film thicknesses of gate thermal oxide films of a plurality of processing circuit portions comprising MOS-transistors; and the film-thickness-difference variation among gate thermal oxide films of the processing circuits comprising the MOS-transistors; within desired ranges without deteriorating the performance of the MOS-transistors.
2. Description of the Prior Art
Those semiconductor devices such as represented by LSI""s and VLSI""s have been developed year by year, concerning increased density, increased integration, enhanced function, and increased processing speed. Achieving increased density of semiconductor devices requires precise structures thereof. Further, achieving increased integration and higher function requires that: (i) different kinds of devices (or circuits) such as processing devices and (ii) semiconductor memory devices (such as non-volatile memory devices), which have been inherently manufactured independently, are to be brought into semiconductor devices collectively mounted on a single plate of semiconductor substrate. Moreover, achieving an increased processing speed requires to reduce the thickness of gate thermal oxide films of MOS-transistors (MOSFET""s).
However, excessively reduced thickness of gate thermal oxide films causes such a phenomenon that electric current (gate leak electric current) flows from a gate electrode to a source electrode or from a gate electrode to a sub-electrode. This phenomenon causes increased power consumption.
Such as in mobile telephones (portable telephones, PHS""s) and household electric appliances, those semiconductor devices to be adopted are required to have such characteristics: to execute faster arithmetic processing in operation; and to have reduced power consumption on stand-by. Since the faster arithmetic processing means or requires increased power consumption, there are required conflicting performances for a single semiconductor device.
FIG. 25 shows a semiconductor device having a structure coping with the conflicting requirements in operation and on stand-by.
Reference numeral 100 designates a semiconductor device constituted of a first processing circuit portion Q1 which operates or works in operation, a second processing circuit portion Q2 which operates on stand-by, and other circuit portion Q3. The first processing circuit portion Q1 has a thinned gate thermal oxide film for enabling a high-speed processing calculation, and the second processing circuit portion Q2 has a thickened gate thermal oxide film for reduced power consumption. For example, both of the gate thermal oxide films of the first processing circuit portion Q1 and second processing circuit portion Q2 are to be preferably deposited to exceed 10 angstroms, at a precision of several angstroms relative to a desired value, and without variance.
Japanese Patent Application Laid-Open No. HEI-2-129968 (129968/1990) discloses a method for implementing those circuit portions within a single semiconductor device which are driven by a plurality of types of power supply voltages, and for differently forming the thicknesses of the gate thermal oxide films of such circuit portions. This manufacturing method shall be detailed hereinafter.
FIGS. 26 through 36 show a conventional manufacturing method of semiconductor devices.
As firstly shown in FIG. 26, there are formed: element-separating insulation films 102 on a one-conductive type of semiconductor substrate 101; a p-type well region 103 in a semiconductor element forming region (hereinafter called xe2x80x9celement forming regionxe2x80x9d) of a first processing circuit portion Q1n; a p-type well region 104 in an element forming region of a second processing circuit portion Q2n; and a p-type well region 105 of a non-volatile memory circuit portion (hereinafter called xe2x80x9cmemory circuit portionxe2x80x9d) Qm.
Next, as shown in FIG. 27, there is grown a first gate thermal oxide film 106 so as to have a thickness of 50 angstroms to 100 angstroms over the whole surface of the semiconductor substrate 101, and then there is formed a first conducting layer 107 over the whole surface of the semiconductor substrate 101 including the first gate thermal oxide film 106. The first conducting layer 107 can be formed such as by growing a polycrystalline silicon film deposited by a CVD (Chemical Vapor Deposition) method. Next, as shown in FIG. 28, the first conducting layer 107 is patterned into a predetermined shape of first conducting layer 107a. This first conducting layer 107a is left in the element forming region of the memory circuit portion Qm only.
Next, as shown in FIG. 28, there is grown an insulating film 108 over the respective surfaces of the first gate thermal oxide film 106 and first conducting layer 107a. This insulating film 108 has a three-layer structure comprising an oxide film, a nitride film and another oxide film such as deposited by a CVD method, and generally called xe2x80x9cONO filmxe2x80x9d.
Next, as shown in FIG. 30, the first gate thermal oxide film 106 and insulating film 108 are patterned into predetermined shapes of first gate thermal oxide film 106a and insulating film 108a, respectively. The first gate thermal oxide film 106a and insulating film 108a are formed to leave the element forming region of the memory circuit portion Qm. At this time, the shape of the first conducting layer 107a is unchanged, since it is covered by the insulating, film 108a. 
Next, as shown in FIG. 31, there is provided a second gate thermal oxide film 109 over the whole surfaces of the element forming regions of the first processing circuit portion Q1n and second processing circuit portion Q2n. This second gate thermal oxide film 109 is rendered to grow into a thickness of 15 to 20 angstroms in the element forming regions. At this time, no second gate thermal oxide films 109 are formed on the insulating film 108a of the memory circuit portion Qm, because of the nature of the ONO film.
Next, as shown in FIG. 32, the second gate thermal oxide film 109 is patterned into a predetermined shape 109a. This second gate thermal oxide film 109a is left in the element forming region of the second processing circuit portion Q2n only.
Next, as shown in FIG. 33, there is grown a third gate thermal oxide film 110 over the element forming regions of the first processing circuit portion Q1n and second processing circuit portion Q2n, such that the third gate thermal oxide film 110 has a thickness between 15 angstroms exclusive to 22 angstroms inclusive in the element forming region of the first processing circuit portion Q1n. At this time, no third gate thermal oxide films are formed on the insulating film 108a of the memory circuit portion Qm because of the nature of the ONO film, whereas the second gate thermal oxide film 109a in the second processing circuit portion Q2n is further deposited so that the thickness exceeds 25 angstroms and reaches 32 angstroms. Further, the shape of the second gate thermal oxide film 109a is also integrated with the third gate thermal oxide film. Thus, the thermal oxide film in the second processing circuit portion Q2n shall be called a xe2x80x9cthird gate thermal oxide film 110axe2x80x9d. 
Next, as shown in FIG. 34, there is formed a second conducting layer 111 over the third gate thermal oxide film 110, third gate thermal oxide film 110a and insulating film 108a. The second conducting layer 111 is formed in the same manner as the first conducting layer 107, such as by growing a polycrystalline silicon film deposited by a CVD (Chemical Vapor Deposition) method.
Next, as shown in FIG. 35, the first gate thermal oxide film 106a, first conducting layer 107a, insulating film 108a, third gate thermal oxide film 110 and third gate thermal oxide film 110a are patterned into predetermined shapes of first gate thermal oxide film 106e, first conducting layer 107e, insulating film 108e, third gate thermal oxide film 110c and third gate thermal oxide film 110d, respectively. Further, the second conducting layer 111 is patterned into predetermined shapes of second conducting layers 111c, 111d, 111e. 
In the above, the third gate thermal oxide film 110c and second conducting layer 111c are provided to form a gate thermal oxide film and a gate electrode of the first processing circuit portion Q1n, while the third gate thermal oxide film 110d and second conducting layer 111d are provided to form a gate thermal oxide film and a gate electrode of the second processing circuit portion Q2n. Further, the first gate thermal oxide film 106e, first conducting layer 107e, insulating film 108e and second conducting layer 111e are provided to form, in the memory circuit portion Qm: a gate thermal oxide film; a lower gate electrode; an insulating film for separating the lower gate electrode and an upper gate electrode of the memory circuit portion Qm; and the upper gate electrode, respectively.
Next, as shown in FIG. 36, there are formed side walls 112 at the respective side surfaces of the first gate thermal oxide film 106e, first conducting layer 107e, insulating film 108e, third gate thermal oxide film 110c, third gate thermal oxide film 110d, second conducting layer 111c, second conducting layer 111d and second conducting layer 111e. The side walls 112 are formed such as by growing an insulating film comprising a silicon oxide film or silicon nitride film by a CVD method, and by conducting anisotropic etching by a RIE (reactive ion etching) method. Further, there is formed a drain region 114, by introducing n-type impurities into the first processing circuit portion Q1n. It is possible to adopt arsenic as the n-type impurities, for example. Further, there are formed a source region 115 and a drain region 116, by introducing n-type impurities into the second processing circuit portion Q2n. Similarly, there are formed a source region 117 and a drain region 118, by introducing n-type impurities into the memory circuit portion Qm. Based on the above, there are formed gate thermal oxide films of different thicknesses in the respective circuit portions, and the memory circuit portion Qm is formed with a plurality of conducting layers in a multi-layered manner.
According to the aforementioned conventional semiconductor devices and the manufacturing method therefore, it is possible to bring the gate thermal oxide film of the first processing circuit portion Q1n and the gate thermal oxide film of the second processing circuit portion Q2n, into thicknesses greater than 10 angstroms and 20 angstroms, respectively. However, conducting mass-production at the setting of 10 angstroms to 20 angstroms tends to cause variance of thickness in the gate thermal oxide films, and makes it difficult to reach a thickness difference of 10 angstroms or less between the two processing circuit blocks.
This is because the thicknesses of the gate thermal oxide films are evenly increased as shown in FIG. 33 in which the second processing circuit portion Q2n is additionally formed with the gate thermal oxide film while the first processing circuit portion Q1n is formed with the gate thermal oxide film.
In this case, it becomes possible to render the intended thickness difference between the second processing circuit portion Q2n and first processing circuit portion Q1n to be limited to 10 angstroms or less, if the second gate thermal oxide film is grown into a thickness of 10 angstroms or less. However, it is difficult to allow a gate thermal oxide film to uniformly grow into a thickness of 10 angstroms or less, including industrial manufacturing errors. Concretely, growing a gate thermal oxide film into a thickness of 10 angstroms or less causes errors of thickness (thickness errors) on the order of xc2x13 angstroms, thereby resulting in an increased error relative to an expected value. These thickness errors cause variance among semiconductor elements, thereby resulting in considerably deteriorated performance of MOS-transistors.
Objects of the Invention
It is therefore an object of the present invention to provide a semiconductor device and a manufacturing method therefore capable of forming various thicknesses of gate oxide films at desired values, without deteriorating the performance of MOS-transistors.
Summary of the Invention
The present invention provides a manufacturing method of a semiconductor device having a single semiconductor substrate, for forming a first processing circuit portion and a second processing circuit portion having mutually different thicknesses of gate oxide films on the single semiconductor substrate including the steps of: forming a first gate oxide film over the semiconductor substrate; sequentially forming an insulating film and a first conducting layer over the entire surface of the first gate oxide film; eliminating those portions ranging from the first gate oxide film to the first conducting layer, which portions are included within an element forming region of the first processing circuit portion; and forming, only in the element forming region of the first processing circuit portion, a second gate oxide film having a thickness different from that of the first gate oxide film.